Field effect transistor using graphene

ABSTRACT

According to example embodiments, a field effect transistor includes a graphene channel layer on a substrate. The graphene channel layer defines a slit. A source electrode and a drain electrode are spaced apart from each other and arranged to apply voltages to the graphene channel layer. A gate insulation layer is between the graphene channel layer and a gate electrode.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application is a divisional of U.S.patent application Ser. No. 13/772,693 filed on Feb. 21, 2013 and claimspriority under 35 U.S.C. §119 to Korean Patent Application No.10-2012-0077368, filed on Jul. 16, 2012, in the Korean IntellectualProperty Office, the disclosure of which is incorporated herein in itsentirety by reference.

BACKGROUND

1. Field

Example embodiments relate to field effect transistors includinggraphene, and more particularly, to field effect transistors includinggraphene as channel layers.

2. Description of the Related Art

Currently, carbon-based materials including fullerene, carbon nanotube,diamond, graphite, and graphene are being researched in various fields.

From among those materials, carbon nanotube has been in the limelightsince the 1990s. However, recently, some attention has been focused ongraphene. Graphene may have a plate-like structure. Graphene is athin-film in which carbon atoms are 2-dimensionally arranged. Sincecharges in graphene may function as zero effective mass particles,graphene may have very high electric conductivity, high heatconductivity, and high elasticity.

Various research has characterized some properties of graphene and/orstudied applications of graphene to various fields. Particularly,Novoselov and Geim have fabricated graphene having a hexagonalstructure, in which carbon atoms are 2-dimensionally arranged, bymechanically peeling off graphene, fabricated a transistor using thesame, and have reported field effect property of graphene. In otherwords, a transistor using graphene features linear increase ofconductivity according to gate voltages.

SUMMARY

Example embodiments relate to high-performance field effect transistorswhich include graphene as channel layers and are capable of having ahigh ON/OFF ratio of operation currents.

Additional aspects will be apparent in the description which followsand, or may be learned by practice of example embodiments.

According to example embodiments, a field effect transistor includes: asubstrate; a graphene channel layer on the substrate, the graphenechannel layer defining a slit; a source electrode and a drain electrodespaced apart from each other, the source electrode and the drainelectrode being configured to apply voltages to the graphene channellayer; a gate electrode on the graphene channel layer; and a gateinsulation layer between the graphene channel layer and the gateelectrode.

In example embodiments, a potential barrier material may fill the slit.The potential barrier material may be configured to induceFowler-Nordheim (F-N) tunneling through the graphene channel layer whena gate voltage is applied to the gate electrode.

In example embodiments, the potential barrier material may includeundoped silicon (Si).

In example embodiments, the potential barrier material and the gateinsulation layer may be a same material.

In example embodiments, a width of the slit may allow F-N tunnelingthrough the graphene channel layer when a gate voltage is applied to thegate electrode.

In example embodiments, the graphene channel layer may define aplurality of the slits.

In example embodiments, the gate electrode may be closer to the slitthan at least one of the source electrode and the drain electrode.

In example embodiments, the source electrode may be closer to the slitthan the drain electrode.

According to example embodiments, a field effect transistor includes: asubstrate; a graphene channel layer on the substrate, the graphenechannel layer defining a slit; a source electrode and a drain electrodespaced apart from each other, the source electrode and the drainelectrode being configured to apply voltages to the graphene channellayer; a gate electrode on the graphene channel layer; and a gateinsulation layer between the graphene channel layer and the gateelectrode, wherein the slit is filled with a potential barrier materialthat is configured to induce Fowler-Nordheim (F-N) tunneling through thegraphene channel layer when a gate voltage is applied to the gateelectrode.

In example embodiments, the potential barrier material may be undopedsilicon (Si).

According to example embodiments, a field effect transistor includes: asubstrate; a graphene channel layer, on the substrate, the graphenechannel layer defining a slit; a source electrode and a drain electrodeon opposite ends of the graphene channel layer; a gate electrode belowthe graphene channel layer; a gate insulation layer between the graphenechannel layer and the gate electrode; and a potential barrier materialfilling the slit of the graphene channel layer, the potential battiermaterial being configured to induce Fowler-Nordheim (F-N) tunnelingthrough the graphene channel layer when a gate voltage is applied to thegate electrode.

In example embodiments, the potential barrier material may be undopedsilicon (Si).

According to example embodiments, a method of fabricating a field effecttransistor includes: forming a graphene channel layer on a substrate;forming a slit in the graphene channel layer; forming a source electrodeand a drain electrode that are spaced apart from each other, the sourceand the drain electrode being configured to apply voltages to thegraphene channel layer; forming a gate electrode on the graphene channellayer; forming a gate insulation layer between the graphene channellayer and the gate electrode; and filling the slit with a potentialbarrier material, the potential barrier material being configured toinduce Fowler-Nordheim (F-N) tunneling through the graphene channellayer when a gate voltage is applied to the gate electrode.

In example embodiments, the forming the slit may include using an e-beamlithography method.

In example embodiments, the potential barrier material and the gateinsulation layer may be formed of a same material.

In example embodiments, the potential barrier material may be undopedsilicon (Si).

According to example embodiments, a field effect transistor includes: asubstrate, a graphene channel layer on the substrate, the graphenechannel layer defining at least one slit; a source electrode and a drainelectrode that are spaced apart on at least one of the graphene layerand the substrate; a gate electrode on the substrate; a gate insulationlayer between the gate electrode and the graphene channel layer.

In example embodiments, the graphene channel layer may define one slit,a potential barrier material may fill the slit of the graphene channellayer, and the potential barrier material may be configured to induceFowler-Nordheim (F-N) tunneling through the graphene channel layer whena gate voltage is applied to the gate electrode.

In example embodiments, the potential barrier material and the gateinsulation layer may be a same material.

In example embodiments, the graphene channel layer may define one slit,the slit of the graphene channel layer may be closer to one of thesource electrode and the drain electrode compared to an other of thesource electrode and the drain electrode.

In example embodiments, the graphene channel layer may be about one toabout three carbon layers in thickness.

In example embodiments, the gate electrode may be between the sourceelectrode and the drain electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

These and/or other aspects will become apparent and more readilyappreciated from the following description of non-limiting embodiments,taken in conjunction with the accompanying drawings. The drawings arenot necessarily to scale, emphasis instead being placed uponillustrating principles of example embodiments. In the drawings:

FIGS. 1A and 1B are schematic diagrams respectively showing carbon atomarrangement of graphene and energy band structure of graphene nearby theFermi energy;

FIG. 2 is a sectional view of a field effect transistor including agraphene channel layer, according to example embodiments;

FIGS. 3A through 3C are energy band diagrams for describing an operationmechanism of the field effect transistor of FIG. 2;

FIG. 4 is a sectional view of a field effect transistor including agraphene channel layer, according to example embodiments;

FIGS. 5A, 5B, and 5C are sectional views of field effect transistorsincluding a graphene channel layer, according to example embodiments;

FIGS. 6A, 6B, and 6C are sectional views of field effect transistorsincluding a graphene channel layer, according to example embodiments;

FIGS. 7A to 7D are sectional views of field effect transistors includinga graphene channel layer, according to example embodiments;

FIG. 8 is a sectional view of a field effect transistor including aplurality of graphene channel layers, according to example embodiments;and

FIG. 9 is a sectional view of a field effect device according to exampleembodiments.

DETAILED DESCRIPTION

Example embodiments will now be described more fully with reference tothe accompanying drawings, in which some example embodiments are shown.Example embodiments, may, however, be embodied in many different formsand should not be construed as being limited to the embodiments setforth herein; rather, these example embodiments are provided so thatthis disclosure will be thorough and complete, and will fully convey thescope of example embodiments to those of ordinary skill in the art. Inthe drawings, the thicknesses of layers and regions are exaggerated forclarity. Like reference numerals in the drawings denote like elements,and thus their description may be omitted.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. As used herein the term “and/or” includesany and all combinations of one or more of the associated listed items.Other words used to describe the relationship between elements or layersshould be interpreted in a like fashion (e.g., “between” versus“directly between,” “adjacent” versus “directly adjacent,” “on” versus“directly on”).

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments. As used herein, the singular forms “a”, “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises” and/or “comprising,” when used in this specification,specify the presence of stated features, integers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups thereof. Expressions such as “atleast one of,” when preceding a list of elements, modify the entire listof elements and do not modify the individual elements of the list.

It will be understood that, although the terms first, second, third,etc., may be used herein to describe various elements, components,regions, layers and/or sections, these elements, components, regions,layers and/or sections should not be limited by these terms. These termsare only used to distinguish one element, component, region, layer orsection from another region, layer or section. Thus, a first element,component, region, layer or section discussed below could be termed asecond element, component, region, layer or section without departingfrom the teachings of example embodiments.

Example embodiments are described herein with reference tocross-sectional illustrations that are schematic illustrations ofidealized embodiments (and intermediate structures) of exampleembodiments. As such, variations from the shapes of the illustrations asa result, for example, of manufacturing techniques and/or tolerances,are to be expected. Thus, example embodiments should not be construed aslimited to the particular shapes of regions illustrated herein but areto include deviations in shapes that result, for example, frommanufacturing. Thus, the regions illustrated in the figures areschematic in nature and their shapes are not intended to illustrate theactual shape of a region of a device and are not intended to limit thescope of example embodiments.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which example embodiments belong. Itwill be further understood that terms, such as those defined incommonly-used dictionaries, should be interpreted as having a meaningthat is consistent with their meaning in the context of the relevant artand will not be interpreted in an idealized or overly formal senseunless expressly so defined herein.

FIGS. 1A and 1B are schematic diagrams respectively showing carbon atomarrangement of graphene and energy band structure of graphene nearby theFermi energy.

Referring to FIG. 1A, graphene has a honeycomb-like structure in whichcarbon atoms are located at vertexes of a hexagon. FIG. 1B shows anenergy band structure regarding a unit cell including two carbon atomsadjacent to each other.

Referring to FIG. 1B, in the energy band structure of graphene, aconduction band and a valance band meet each other at each of valleys ofBrillouin zone having a hexagonal structure in k space, and the energyband structure of graphene has a conic shape nearby the Fermi energy.Energy of charges is proportional to momentum, which is similar todispersion relation of photons having no mass. In other words, effectivemass of electrons in graphene may become zero, and carrier mobility ingraphene may be very fast (in Fermi speed about 1/300 of speed oflight). The carrier mobility in graphene may be very high, for examplefrom about 20,000 cm²/Vs to about 200,000 cm²/Vs. Therefore, graphenemay be applied to field effect transistors and high-speed switchingdevices.

Meanwhile, graphene may have a zero band gap type energy band.Therefore, if graphene is used as a channel of a field effecttransistor, high current may flow even in OFF state where no voltage isapplied to a gate, and thus an ON/OFF ratio of an operation current maybe very low. To fabricate a high-performance transistor, it is desirableto raise an ON/OFF ratio of an operation current.

FIG. 2 is a sectional view of a field effect transistor 200 including agraphene channel layer, according to example embodiments.

Referring to FIG. 2, the field effect transistor 200 includes asubstrate 210, a graphene channel layer 230 that is arranged on thesubstrate 210 and includes a slit 235, a source electrode 271 and adrain electrodes 272 that are arranged to apply voltages to the graphenechannel layer 230 and are apart from each other, a gate electrode 273that is arranged to form an electric field on the graphene channel layer230, and a gate insulation layer 250 that is arranged between thegraphene channel layer 230 and the gate electrode 273.

The substrate 210 may be formed of any of various materials on whichgraphene may be formed. For example, the substrate 210 may be formed ofany of silicon (Si), silicon-germanium (SiGe), silicon carbide (SiC),glass, plastics, etc. Furthermore, the substrate 210 may include anepitaxial layer, a silicon-on-insulator (SOI) layer, asemiconductor-on-insulator (SEOI) layer, etc. However, exampleembodiments are not limited thereto.

The graphene channel layer 230 may be a single- or multi-layeredstructure of about one to about three carbon atoms in thickness, butexample embodiments are not limited thereto.

The graphene channel layer 230 may contain graphene having the structureand the energy band as respectively shown in FIGS. 1A and 1B. Thegraphene channel layer 230 may be formed using a micro-mechanicalmethod, thermal decomposition of SiC crystals, chemical vapor deposition(CVD), etc.

The micro-mechanical method is a method of obtaining graphene byattaching an adhesive tape to a graphite sample, detaching the adhesivetape from the graphite sample, and collecting graphene peeled off thegraphite.

The principle of the thermal decomposition of SiC crystals is that, whena SiC monocrystal is heated, SiC on surfaces of the SiC crystal isdecomposed, and Si is removed and graphene is formed of the remainingcarbon (C).

Synthesis of graphene using CVD is described below.

First, a silicon wafer having a silicon oxide (SiO₂) layer is prepared.Next, a metal catalyst layer is formed by depositing a metal catalyst,such as nickel (Ni), copper (Cu), aluminum (Al), iron (Fe), etc., ontothe SiO₂ layer by using a sputtering device or an e-beam evaporator.

Next, the silicon wafer having formed thereon the metal catalyst layerand a carbon-containing gas (CH₄, C₂H₂, C₂H₄, CO, etc.) are suppliedinto a reactor for thermo-chemical vapor deposition or inductive coupledplasma chemical vapor deposition (ICP-CVD) and are heated, such thatcarbon is absorbed to the metal catalyst layer. Next, graphene issynthesized by separating carbon from the metal catalyst layer byrapidly cooling the silicon wafer including the metal catalyst layer andcrystallizing the separated carbon.

Methods for forming the graphene channel layer 230 are not limited tothe methods of synthesizing graphene as described above, and thegraphene channel layer 230 may be formed of any of various methods.Furthermore, the graphene channel layer 230 may be formed bysynthesizing graphene and transferring the graphene to another substrateor a film.

Referring back to FIG. 2, the graphene channel layer 230 includes afirst area 231, a second area 232, and the slit 235. The slit 235 may beformed by using e-beam lithography method. In other words, photoresist(PR) is applied onto the graphene channel layer 230, the photoresist isexposed by using a mask having formed thereon a slit pattern, and the PRis selectively etched. Next, the slit 235 may be patterned by using ane-beam equipment. However, a method of forming the slit 235 is notlimited thereto, and the slit 235 may be formed by using any of variousmethods.

The slit 235 may be filled with a potential barrier material, such thatFowler-Nordheim (F-N) tunneling of electrons may occur between the firstarea 231 and the second area 232 when a gate voltage is applied. The F-Ntunneling effect will be described later. The potential barrier materialmay be a material of which Fermi potential is similar to that ofgraphene when gate voltage is applied. More particularly, the potentialbarrier material may include a semiconductor such as Si, germanium (Ge),SiC, aluminum nitride (AlN), gallium nitride (GaN), gallium phosphide(GaP), GaAs, CdS, ZnSe, CdTe, etc.

The potential barrier material filling the slit 235 may be formed byusing a deposition method, such as epitaxial growth, CVD,plasma-enhanced CVD (PECVD), low pressure CVD, physical vapor deposition(PVD), sputtering, atomic layer deposition (ALD), etc. The potentialbarrier material may fill the slit 235 and may be additionally formed onthe graphene channel layer 230. The potential barrier material formed onthe graphene channel layer 230 may be removed if necessary.

Furthermore, a width w of the slit 235 may be a width for inducing F-Ntunneling of electrons between the first area 231 and the second area232 when a voltage is applied to the gate electrode 273, e.g., fromseveral nm to dozens of nm.

The slit 235 may be formed at the center of the graphene channel layer230. Alternatively, as shown in FIG. 5B, a field effect transistor 500 baccording to example embodiments may be the same as the field effecttransistor 200 in FIG. 2, except the slit 235 of the graphene channellayer 230 b may be formed at a location that is closer to the sourceelectrode 271 than the drain electrode 272. Alternatively, as shown inFIG. 5C, a field effect transistor 500 c according to exampleembodiments may be the same as the field effect transistor 200 in FIG.2, except the slit 235 of the graphene channel layer 230 c may be formedat a location that is closer to the drain electrode 272 than the sourceelectrode 271. Furthermore, as shown in FIG. 5A, a field effecttransistor 500 a according to example embodiments may be the same as thefield effect transistor 200 in FIG. 2, except the graphene channel layer230 may include a plurality of slits 235. In this case, materialsfilling the slits 235 and widths w of the slits 235 may vary from oneanother.

The source electrode 271 and the drain electrode 272 may be electricallyconnected to each other via the graphene channel layer 230. The sourceelectrode 271 and the drain electrode 272 may contain a conductivematerial. For example, the source electrode 271 and the drain electrode272 may be formed of a metal, a metal alloy, a conductive metal oxide,or a conductive metal nitride. More particularly, the source electrode271 and the drain electrode 272 may contain at least one from amongaluminum (Al), gold (Au), beryllium (Be), bismuth (Bi), cobalt (Co),copper (Cu), hafnium (Hf), indium (In), manganese (Mn), molybdenum (Mo),nickel (Ni), lead (Pb), palladium (Pd), platinum (Pt), rhodium (Rh),rhenium (Re), ruthenium (Ru), tantalum (Ta), tellurium (Te), titanium(Ti), tungsten (W), zinc (Zn), and zirconium (Zr). The source electrode271 and the drain electrode 272 may have a single layer structure or amulti-layer structure. The source electrode 271 and the drain electrode272 may be formed by using a deposition method, such as CVD, PECVD, lowpressure CVD, (PVD), sputtering, ALD, etc. The source electrode 271 andthe drain electrode 272 may be replaced with each other.

The gate electrode 273 may contain a conductive material and may beformed of a metal, a metal alloy, a conductive metal oxide, or aconductive metal nitride, and combinations thereof. The metal mayinclude at least one from among Al, Au, Be, Bi, Co, Cu, Hf, In, Mn, Mo,Ni, Pb, Pd, Pt, Rh, Re, Ru, Ta, Te, Ti, W, Zn, and Zr. Furthermore, thegate electrode 273 may be formed of a semiconductor material doped withan impurity. The gate electrode 273 may be formed by using a depositionmethod, such as CVD, PECVD, low pressure CVD, (PVD), sputtering, ALD,etc.

The gate insulation layer 250 is formed between the gate electrode 273and the graphene channel layer 230. The gate insulation layer 250 maycontain an insulation material, e.g., silicon, a silicon oxide, asilicon nitride, or a silicon oxynitride. Furthermore, the gateinsulation layer 250 may be a composite layer having a double-layerstructure including a silicon oxide layer and a silicon nitride layer ormay be a partially nitrified silicon oxide layer. The nitrification maybe performed by using any of methods, such as annealing, rapid thermalannealing, or laser RTA, by using a gas containing nitrogen, e.g., NH₃gas. Furthermore, the nitrification may be performed by using any ofother methods, such as plasma nitrification, plasma ion implantation,plasma enhanced CVD (PECVD), high-density plasma CVD (HDP-CVD), andradical nitrification. After the nitrification, the structure may bethermally treated in inert atmosphere containing an inert gas, such ashelium or argon. A surface of the nitrified structure may face the gateelectrode 273. Furthermore, the gate insulation layer 250 may be formedof the same material as the material filling the slit 235.

FIGS. 3A through 3C are energy band diagrams for describing operationmechanism of the field effect transistor 200 of FIG. 2.

FIG. 3A shows energy change in the graphene channel layer 230 when agate voltage is applied to the field effect transistor 200. Referring toFIG. 3A, when a positive (+) gate voltage is applied to the gateelectrode 273, the Fermi potential of the graphene channel layer 230rises toward the conduction band from E0 to E1, and thus a number ofconduction electrons increases. On the contrary, when a negative (−)gate voltage is applied to the gate electrode 273, the Fermi potentialof the graphene channel layer 230 decreases toward the valence band fromE0 to E2, and thus a number of conduction holes increases. In otherwords, based on polarity of a voltage applied to the gate electrode 273,charges may be induced in the graphene channel layer 230 and the Fermilevel of graphene may be shifted.

FIG. 3B shows energy level of graphene at the first area 231, the secondarea 232, and the slit 235 of the graphene channel layer 230 when nodrain voltage and no gate voltage are applied to the field effecttransistor 200 of FIG. 2. The initial Fermi potential of the graphenechannel layer 230 is E0.

FIG. 3C shows energy level of graphene when drain voltage is applied tothe field effect transistor 200 of FIG. 2 and no gate voltage is appliedthereto, that is, energy level of graphene in OFF state. As the drainvoltage is applied, the energy levels of the slit 235 and the secondarea 232 are tilted. However, due to potential barrier formed by theslit 235, electrons hardly move between the first area 231 and thesecond area 232.

FIG. 3D shows energy level of graphene when drain voltage and gatevoltage are applied to the field effect transistor 200 of FIG. 2, thatis, energy level of graphene in ON state. As the gate voltage applied,the Fermi potential in graphene rises. If the Fermi potential ingraphene is higher than the potential barrier formed by the slit 235,electrons in the graphene channel layer 230 may easily move from thefirst area 231 to the second area 232. The movement is indicated with asolid line. Furthermore, electrons in the first area 231, that is,electrons at the source side may tunnel through a triangular potentialbarrier. The tunneling is referred to as Fowler-Nordheim tunneling (F-Ntunneling). Movement of electrons via the F-N tunneling is indicatedwith a broken line arrow. In case of the F-N tunneling, the width oftunneling barrier is narrow. Therefore, F-N tunneling may occur easierthan direct tunneling. Here, the term direct tunneling refers totunneling that occurs before a potential barrier is deformed by the slit235.

The above description of operation of the field effect transistor 200 isgiven in relation to a case in which a positive gate voltage is applied.However, even if a negative gate voltage is applied, operation of thefield effect transistor 200 may be same as described above except thatholes function as carriers.

FIG. 4 is a sectional view of a field effect transistor 400 including agraphene channel layer 430, according to example embodiments.

Referring to FIG. 4, the field effect transistor 400 includes asubstrate 410, a graphene channel layer 430 that is arranged on thesubstrate 410 and includes a slit 435, a source electrode 471 and adrain electrode 472 that are arranged to apply voltages to the graphenechannel layer 430 and are apart from each other, agate electrode 473that is arranged to form an electric field on the graphene channel layer430, and a gate insulation layer 450 that is arranged between thegraphene channel layer 430 and the gate electrode 473.

The field effect transistor 400 of FIG. 4 is identical to the fieldeffect transistor 200 of FIG. 2 except that the gate electrode 473 andthe gate insulation layer 450 are formed below the graphene channellayer 430.

The graphene channel layer 430 may be a single- or multi-layeredstructure of about one to about three carbon atoms in thickness, butexample embodiments are not limited thereto.

The gate electrode 473 may contain a conductive material and may beformed of a metal, a metal alloy, a conductive metal oxide, or aconductive metal nitride, and combinations thereof. To form the gateelectrode 473, a groove may be formed in the substrate 410, and the gateelectrode 473 may be formed by using any of various thin-film depositionmethods. Alternatively, after the gate electrode 473 is formed withoutforming a groove in the substrate 410, the gate insulation layer 450 maybe formed to surround the gate electrode 473. Furthermore, to apply avoltage to the gate electrode 473, a via hole may be formed in the fieldeffect transistor 400.

The slit 435 may be formed at the center of the graphene channel layer430. Alternatively, as shown in FIG. 6B, a field effect transistor 600 baccording to example embodiments may be the same as the field effecttransistor 400 in FIG. 4, except the slit 435 of the graphene channellayer 430 b may be formed at a location that is closer to the sourceelectrode 471 than the drain electrode 472. Alternatively, as shown inFIG. 6C, a field effect transistor 600 c according to exampleembodiments may be the same as the field effect transistor 400 in FIG.4, except the slit 435 of the graphene channel layer 430 c may be formedat a location that is closer to the drain electrode 472 than the sourceelectrode 471. Furthermore, as shown in FIG. 6A, a field effecttransistor 600 c according to example embodiments may be the same as thefield effect transistor 400 in FIG. 2, except the graphene channel layer430 may include a plurality, of slits 435. In this case, materialsfilling the slits 435 and widths w of the slits 435 may vary from oneanother.

FIGS. 7A to 7D are sectional views of field effect transistors includinga graphene channel layer, according to example embodiments.

Referring to FIG. 7A, according to example embodiments, a field effecttransistor 700 a may be the same as the field effect transistor 200 inFIG. 2, except for the arrangement of the source electrode 271 and/orthe drain electrode 272. As shown in FIG. 7A, the source electrode 271and the drain electrode 272 may be on the substrate 210 and contactsides of the graphene channel layer 730 a.

Referring to FIG. 7B, according to example embodiments, a field effecttransistor 700 b may be the same as the field effect transistor 400 inFIG. 4, except for the arrangement of the source electrode 471 and/orthe drain electrode 472. As shown in FIG. 7B, the source electrode 471and the drain electrode 472 may be on the gate insulation layer 450 andcontact sides of the graphene channel layer 730 b.

Referring to FIG. 7C, according to example embodiments, a field effecttransistor 700 c may be the same as the field effect transistor 200 inFIG. 2, except for the arrangement of the source electrode 771 c and/orthe drain electrode 772 c. As shown in FIG. 7C, the source electrode 771c and the drain electrode 772 c may be on the substrate 210 and thegraphene channel layer 730 c so the source electrode 771 c and the drainelectrode 772 contact sides of the graphene channel layer 730 c.

Referring to FIG. 7D, according to example embodiments, a field effecttransistor 700 d may be the same as the field effect transistor 400 inFIG. 4, except for the arrangement of the source electrode 771 d and/orthe drain electrode 772 d. As shown in FIG. 7D, the source electrode 771d and the drain electrode 772 d may be on the gate insulation layer 450and the substrate 410 so the source electrode 771 d and the drainelectrode 772 d contact sides of the graphene channel layer 730 d.

While FIGS. 7A to 7D illustrate field effect transistors 700 a to 700 d,where the graphene channel layers 730 a to 730 d have a slit (235 or435) in the middle of the graphene channel layers 730 a to 730 d,example embodiments are not limited thereto. For example, the graphenechannel layers 730 a to 730 d of FIGS. 7A to 7D alternatively could bemodified to include a graphene channel layer having a plurality of slitsor a graphene channel layer have a slit that is closer to one of thesource and drain electrodes, as shown in FIGS. 5A to 5C and FIGS. 6A to6C.

FIG. 8 is a sectional view of a field effect transistor including aplurality of graphene channel layers, according to example embodiments.

Referring to FIG. 8, according to example embodiments a field effecttransistor 800 may be the same as the field effect transistor 400 inFIG. 4, except the field effect transistor 800 further includes aninsulating layer 350 on the graphene channel layer 430, a secondgraphene channel layer 830 having a slit 835 on the insulating layer350, a second gate insulating layer 850 on the second graphene channellayer 830, and a second gate electrode 873 on the second graphenechannel layer 830. A material of the insulating layer 350 and secondinsulating layer 850 may be the same as a material of the gateinsulating layer 450. A material of the gate electrode 873 may be thesame as a material of the gate electrode 873.

While FIG. 8 illustrates a field effect transistor 800, where thegraphene channel layers 830 and 430 have a slit (835 or 435) in themiddle of the graphene channel layers 830 and 430, example embodimentsare not limited thereto. For example, the graphene channel layers 830and 430 of FIG. 8 alternatively could be modified to include a graphenechannel layer having a plurality of slits or a graphene channel layerhave a slit that is closer to one of the source and drain electrodes, asshown in FIGS. 5A to 5C and 6A to 6C.

FIG. 9 is a sectional view of a field effect device according to exampleembodiments.

Referring to FIG. 9, according to example embodiments, a field effectsystem may include a substrate 910, a plurality of gate electrodes 973positioned in grooves of the substrate 910, a plurality of gateinsulating layers 950 on the gate electrodes 973, a graphene channellayer 930 on the substrate 910, and a plurality of first electrodes 971and second electrodes 972 alternately spaced apart on the graphenechannel layer 930. The graphene channel layer 930 may include aplurality of slits 935, similar to the slits 235 and 435 discussed abovewith reference to FIGS. 2 and 4.

As described above, since the field effect transistors 200 and 400include slits that are filled with materials for forming potentialbarriers on the graphene channel layers 230 and 430, electrons mayhardly move in OFF state. However, in ON state, the field effecttransistors 200 and 400 operate according to material properties ofgraphene. As a result, ON/OFF ratios of operation currents of the fieldeffect transistors 200 and 400 increase.

The field effect transistors 200, 400, 500 a, 500 b, 500 c, 600 a, 600b, 600 c, 700 a, 700 b, 700 c, 700 d, and 800 described above areprovided as examples of field effect transistors with improved qualitydue to the graphene channel layers including slits (e.g., 230, 430).However, detailed structures thereof may vary. For example, eachthin-film layer may be formed to have a multi-layer structure instead ofthe single layer structure as shown herein.

It should be understood that example embodiments described herein shouldbe considered in a descriptive sense only and not for purposes oflimitation. Descriptions of features or aspects within each embodimentshould typically be considered as available for other similar featuresor aspects in other embodiments. While some example embodiments havebeen particularly shown and described, it will be understood by one ofordinary skill in the art that variations in form and detail may be madetherein without departing from the spirit and scope of the claims.

1-10. (canceled)
 11. A method of fabricating a field effect transistor,the method comprising: forming a graphene channel layer on a substrate;forming a slit in the graphene channel layer; forming a source electrodeand a drain electrode that are spaced apart from each other, the sourceand the drain electrode being configured to apply voltages to thegraphene channel layer; forming a gate electrode on the graphene channellayer; forming a gate insulation layer between the graphene channellayer and the gate electrode; and filling the slit with a potentialbarrier material, the potential barrier material being configured toinduce Fowler-Nordheim (F-N) tunneling through the graphene channellayer when a gate voltage is applied to the gate electrode.
 12. Themethod of claim 11, wherein the forming the slit includes using e-beamlithography.
 13. The method of claim 11, wherein the potential barriermaterial and the gate insulation layer are a same material.
 14. Themethod of claim 11, wherein the potential barrier material includesundoped silicon (Si). 15-20. (canceled)